The invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to capacitor-transistor strap connections for a memory cell and methods for making such capacitor-transistor strap connections.
Dynamic random access memory (DRAM) devices are the most commonly used type of semiconductor memory and, thus, are found in many integrated circuit designs. A generic DRAM includes a plurality of substantially identical memory cell arrays, a plurality of bit lines, and a plurality of word lines that intersect the bit lines. Each individual memory cell array includes a plurality of memory cells arranged in rows and columns. Each individual memory cell includes a capacitor for storing data in the form of charges and an access device, such as a field effect transistor (FET), for allowing the transfer of charge to, and from, the capacitor during read and write operations. Each memory cell in the array is located at the intersection of one of the word lines and one of the bit lines. Either the source or drain of the access device is connected to one of the bit lines and the gate of the access device is connected to one of the word lines.
A variety of field effect transistor, known as a fin-type field effect transistor (FinFET), may be used as an access device in a memory cell. A FinFET may be fabricated using a silicon-on-insulator (SOI) wafer that includes a device layer of a single crystal semiconductor, such as silicon. Each FinFET includes a narrow vertical semiconductor body or fin fashioned from the device layer. A conductive gate electrode intersects a channel of the fin and is isolated electrically from the fin by a thin gate dielectric layer. The opposite ends of the fin, which are not covered by the gate electrode, are heavily doped to define a source and a drain. When a voltage exceeding a characteristic threshold voltage is applied to the gate electrode, charge carriers flow through the channel between the source and drain to create an output current that may be used in read and write operations.
Improved capacitor-transistor strap connections for a memory cell and methods for making such capacitor-transistor strap connections are needed.